A typical analog to digital converter (ADC) has a track and hold circuit that samples an analog input signal. The track and hold circuit operates in either a track mode or a hold mode. In an ADC consisting of a preamplifier and a comparator, normally the track and hold circuit tracks the input signal in half of the clock cycle and holds the signal in the rest of the clock cycle to convert an analog level to a digital code. The typical ADC wastes power during the track mode because the ADC is powered but does not produce a change in an ADC output.
The ADC output changes state only during the hold mode, a transition through an ADC reference voltage by the track and hold circuit output, and clocking of the ADC. A clock circuit clocks the ADC output to produce a possible change in ADC output only when the track and hold circuit is in the hold mode and not in the track mode. Thus, the ADC output cannot change state during the track mode. However, during the track mode, an amplifier, a comparator, and other ADC subcircuits consume power. Therefore, the ADC wastes power during the track mode.
What is needed is an apparatus and method to reduce ADC power consumption during the track mode as well as overcome other shortcomings noted above.